1. Field of the Invention
The invention relates to a delta modulator, and particularly to a delta modulator which can dynamically adjust number of bits solved or quantization step size to accomplish the function of differential sample and analog-to-digital conversion.
2. Description of the Prior Art
The conventional sample-and-hold circuit and the feedback integrator also referred to as digital-to-analog converter are the independent circuits respectively, and each circuit is connected to positive/negative input terminal of the comparator. In the design, the offset of comparator shall keep fixed under different common-mode voltage. The feedback integrator or the digital-to-analog converter adopts current/voltage integration mode, which is apt to be influenced by the jitter of clock, and the distortion of output signal will be occurred. The current sources and voltage sources shall be matched perfectly to avoid the output voltage drift of integrator. The feedback integrator or the digital-to-analog converter alters the charge-discharge frequency to dynamically adjust quantization step size, but an additional clock source higher than the sampling frequency is required.
Please refer to the prior art shown in FIG. 1A, and refer to U.S. Pat. No. 3,761,841, two input terminals of the comparator 23 are respectively connected with the input signal and the output of the integrator composed of the resistor R1 and the capacitor C1. The feedback trigger 19 takes the sample from the output of the comparator 23 at fixed frequency. The current source S1 (current: 2I) and current source S2 (current: I) are used to increase or decrease a step size.
Please refer to the prior art shown in FIG. 1B, which exhibits normal output of the integrator composed of the resistor R1 and the capacitor C1. In the unused channel, the output voltage of the integrator composed of the resistor R1 and the capacitor C1 will be drifted, as the prior art shown in FIG. 1C, the ratio of current source S1 (current: 2I) and current source S2 (current: I) is not 2 to 1 due to the mismatch reason. The feedback trigger 17 dynamically adjusts the magnitude of current source S2 through the output of the integrator composed of the resistor R2 and the capacitor C2. The sampling frequency of the feedback trigger 17 equals to that of the feedback trigger 19, but there is a fixed phase difference. In order to prevent the mismatch of current source S1 and current source S2 and the integration time constant constituted by resistor R2 and capacitor C2 will be greater than the sampling period.
The structure shown in FIG. 1A adopts successive time to rebuild the signal (composed of S1, S2, R1, R2, C1, C2), which is apt to be influenced by the clock jitter, the integration time error will be generated. Under different common-mode voltage, the offset of the comparator won't be constant. If the input signal frequency is low, the integration constant needed by the integrator shall be high, so that large capacitor or large resistor (R1, C1, R2, C2) will be required. When the channel is unused, because the ratio of current source S1 (current: 2I) and current source S2 (current: I) is not 2 to 1, the output of the integrator composed of the resistor R1 and the capacitor C1 will be drifted, then a calibration circuit (composed of trigger 17, resistor R2, capacitor C2) will be required.
Please refer to the ordinary skill in the prior art shown in FIG. 2, and refer to U.S. Pat. No. 3,706,944, two terminals of the comparator 19 are respectively connected with the input signal Ein and the output of the integrator 28. The sampling pulse generator 21 takes the sample from the output of the flip flop 20. If the value of output signal E20 is logic ‘0’, the logic gate 22 will output a negatively quantized step. If the value of the digital output signal E20 is logic ‘1’, the logic gate 22 will output a positively quantized step. The digital output signal E20 judges whether the quantization step size is needed to be adjusted through the adaption logic 24. The output signal of the adaption logic 24 controls the output of the counter 25, and further controls the output frequency E26 of the pulse rate selector 26. The frequency ratio of E25 to E21 is used as the adjustment factor. The input signal E28 is rebuilt by repeatedly accumulating the unit step size, particularly the number of repetitions is decided according to the value of the adjustment factor. Redistribution ratio of C− to (C−+CI) multiplied by the output voltage of logic gate 22 or 23 is defined as the unit step size.
Please refer to FIG. 2. The above-mentioned structure needs a high-frequency clock 27 to produce different frequency output ratio. The offset of the comparator 19 won't keep fixed under different common voltage.
Therefore, in order to produce more efficient delta-modulated device to provide better operation efficiency and lower manufacturing cost, it is necessary to develop a delta-modulated device for applying in voice, image, biomedical signal, and radio sensing etc. The purpose is to compress data and save power consumption for an analog-to-digital converter.